Preface
When we constrain the FPGA project, we often see such level standards, such as LVCOM18, LVCOS25, LVDS, LVDS25, etc. In fact, these are a series of level standards, in order to have a deeper understanding of the level standards, the following excerpts from the book "The FPGA Way" for the explanation of the level standards to understand.

Dual Threshold Standard

The so-called dual-threshold standard, is for digital circuits, digital circuits represent the level of only 1 and 0 two states, in the actual circuit, you need to agree on what kind of voltage for 1, what kind of voltage for 0. Digital circuits in the dual-threshold is defined, for example, the TTL.

Interface level standard:

For outputs, the voltage requirement for state 1 is greater than or equal to 2.4V, and the voltage requirement for state 0 is less than or equal to 0.5V;

For inputs, state 1 is required to be greater than or equal to 2.0V and state 0 is required to be less than or equal to 0.8V;
This means that a threshold value greater than a certain value is required to indicate level 1, and a threshold value less than a certain value is required to indicate level 0.
Some interface level standards are described in detail below:

TTL
TTL is an acronym for Transistor-Transistor Logic, and as you can see from its name, the original intent of this interface level standard was to be used between digital systems based on transistor structures.

Digital circuits operating under the TTL interface standard should have a standard power supply of 5V for the internal active devices, with the following output and input conditions:
For the outputs, the voltage requirement for state 1 is greater than or equal to 2.4V, and the voltage requirement for state 0 is less than or equal to 0.5V;

For the input terminal, the judgment requirement of state 1 is greater than or equal to 2.0V, and the judgment requirement of state 0 is less than or equal to 0.8V; Comparison of the output and input voltage requirements,

it can be seen that the output voltage output requirements than the input side of the dual-valve determination standard is more
stringent, which is mainly to take into account the interference of the noise and the transmission speed of the electrical signal between the output and input, so as to make the dual-valve determination standard more reliable.

LVTTL

Because there is a large space between 2.4V and 5V, which does not have any significant benefit in improving noise interference, but also increases the power consumption of the system, and due to the large level difference between the digital state 1, 0, but also affects the response speed of the digital circuit. Therefore, later on the TTL voltage range for some compression, thus forming the LVTTL - Low Voltage Transistor-Transistor Logic, that is, low-voltage TTL level standard. The following describes two LVTTL standards that are currently in common use:

LVTTL3V3
LVTTL3V3 means that the standard power supply for its internal active devices is 3.3V, and the output and input conditions are as follows:
For the output, the voltage requirement for state 1 is greater than or equal to 2.4V, and the voltage requirement for state 0 is less than or equal to 0.4V;

For the input, the judgment requirement for state 1 is greater than or equal to 2.0V, and the judgment requirement for state 0 is less than or equal to 0.8V;
Comparison of the output and input voltage requirements can be seen, in order to ensure the stability of the two-valve determination and noise immunity, the output voltage requirements are still more stringent than the input side of the two-valve determination of the standard, this point is the same for all the digital system interface standards, and will not be repeated later.

LVTTL2V5
LVTTL2V5 means that the standard power supply of the internal active device is 2.5V, and the output and input are as follows:
For the output, the voltage requirement for state 1 is greater than or equal to 2.0V, and the voltage requirement for state 0 is less than or equal to 0.2V;
For the inputs, the determination requirement for state 1 is greater than or equal to 1.7V, and the determination requirement for state 0 is less than or equal to 0.7V.

CMOS
CMOS is the acronym for Complementary Metal Oxide Semiconductor, and from its naming it can be seen that the original intention of this interface level standard is used between digital systems based on NMOS, PMOS composed of MOS tube structure.
Digital circuits working under the CMOS interface standard have a standard power supply of 5V for the internal active devices, and the output and input conditions are as follows:
For the output side, the voltage requirement for state 1 is greater than or equal to 4.45V, and the voltage requirement for state 0 is less than or equal to 0.5V;

For the input side, the judgment requirement of state 1 is greater than or equal to 3.5V, and the judgment requirement of state 0 is less than or equal to 1.5V.

CMOS has a much larger noise tolerance compared to TTL interfaces and its input impedance is much larger than the TTL input impedance.

LVCOMS
Like TTL, CMOS has similarly spawned the LVCMOS interface standard in view of power consumption and response speed considerations, and because MOS tubes have a much lower turn-on threshold relative to transistors, LVCMOS is easier to communicate with using lower voltages than LVTTL. The following describes several LVTTL standards in common use today:

LVCOMS3V3
LVCMOS3V3 means that the standard power supply for its internal active devices is supplied at 3.3 V. The output and input conditions are as follows:
For the output side, the voltage requirement for state 1 is greater than or equal to 3.2V, and the voltage requirement for state 0 is less than or equal to 0.4V;
For the inputs, the determination requirement for state 1 is greater than or equal to 2.0V, and the determination requirement for state 0 is less than or equal to 0.7V.

LVCOMS2V5
LVCMOS2V5 means that the standard power supply of its internal active device is supplied at 2.5V, and the output and input conditions are as follows:
For the output side, the voltage requirement for state 1 is greater than or equal to 2.0V, and the voltage requirement for state 0 is less than or equal to 0.4V;
For the inputs, the determination requirement for state 1 is greater than or equal to 1.7V, and the determination requirement for state 0 is less than or equal to 0.7V.

LVCOMS1V8
LVCMOS1V8 means that the standard power supply for its internal active device is VCC=1.8V, which of course has a certain tolerance, but unlike the level standard introduced before, this tolerance affects its output and input conditions, which are introduced as follows:
For the output, the voltage requirement for state 1 is greater than or equal to VCC-0.45V (or 1.35V if VCC is precisely equal to 1.8V), and the voltage requirement for state 0 is less than or equal to 0.45V;
For the inputs, the determination of state 1 requires greater than or equal to 0.65 times VCC (or 1.17V if VCC is precisely equal to 1.8V), and the determination of state 0 requires less than or equal to 0.35 times VCC (or 0.63V if VCC is precisely equal to 1.8V).

LVCOMS1V5
The meaning of LVCMOS1V5, i.e., the standard power supply for its internal active devices is VCC=1.5V, and its tolerance also affects its output and input conditions, as described below:
For the output side, LVCMOS1V5 does not have a clear requirement, but certainly the closer the state 1 is to VCC, the better, and the closer the state 0 is to 0V, the better;
For the input side, the determination of state 1 is required to be greater than or equal to 0.65 times VCC (or 0.975V if VCC is precisely equal to 1.5V), and the determination of state 0 is required to be less than or equal to 0.35 times VCC (or 0.525V if VCC is precisely equal to 1.5V).

LVCOMS1V2
LVCMOS1V2 means that the standard power supply for its internal active devices is supplied with VCC=1.2V, and its tolerance also affects its output and input conditions, as described below:
For the output side, LVCMOS1V2 also does not have a clear requirement, but certainly the closer the state 1 is to VCC, the better, and the closer the state 0 is to 0V, the better;
For the input side, the determination of state 1 is required to be greater than or equal to 0.65 times VCC (or 0.78V if VCC is precisely equal to 1.2V), and the determination of state 0 is required to be less than or equal to 0.35 times VCC (or 0.42V if VCC is precisely equal to 1.2V).

LVDS
LVDS is the abbreviation of Low Voltage Differential Signaling, i.e. Low Voltage Differential Signaling, and its input and output are different from the interface levels previously described, and it requires two wires to complete the communication. Its working principle is shown in the figure below:

Insert picture description here
The left part of the above figure is the LVDS output, which has an internal constant current source IS that outputs a current value of about constant 3.5-4mA. The rightmost Vout is connected to the input of the LVDS, and a matching resistor with a resistance value of 100 ohms is connected in parallel near the input R. By changing the position of the double-knife, double-throw switch in the above figure, the direction of the current on the differential line is changed to indicate the digital states 0 and 1, so that the differential line on the receiving end will show ±350mV differential level due to the difference in the direction of the current, and is used as a judgment of the digital state in turn. Therefore, the differential level of ± 350mV will be displayed on the differential line at the receiver due to the difference in current direction, and will be used as the basis for the determination of the digital state. There is also a DC bias voltage source VS on the right side of the above figure, which is mainly used to illustrate that the two ends of Vout are in fact generally positive voltage, and there is no such item in the actual circuit. Because the voltage swing of LVDS is only about 350mV, the current is only about 3.5mA, and differential transmission, so it has high speed, ultra-low power consumption, low noise and low cost and other good characteristics.

RS232
RS232 is the U.S. Electronic Industry Association EIA (known as the Electronic Industry Association) developed a serial physical interface standard. RS is the abbreviation of Recommended Standard, the Chinese meaning of the recommended standards, 232 for the identification number. RS232 bus standard has a total of 25 signal lines, here! We only discuss its digital level interface determination standard.
The standard power supply of RS232 is ±12V or ±15V, the voltage requirement of state 1 is between -15V and -3V, and the voltage requirement of state 0 is between 3V and 15V.

RS485
RS485 is equivalent to the upgraded version of RS232, similar to LVDS, RS485 also uses the form of differential to transfer information (but RS485 is really passed two voltage signals to the past), so the anti-jamming is better than RS232. here, we are also only concerned about its digital level interface determination standard.

RS485 state 1, the voltage difference between the two lines is required to be between 2V and 6V; state 0, the voltage difference between the two lines is required to be between -6V and -2V.

Can different standards be mixed?

The above introduces a variety of interface level standards between digital systems, usually in use, it is still strongly recommended that you choose the same standard for both sides of the digital system interface. However, sometimes limited by some of the configuration of the two parties, may not be able to find a unified level standard for communication, then, in addition to the design of the interface conversion circuit boards in addition to no other way? No, in fact, some different interface level standards are compatible.

First of all, single-ended and differential is not compatible, because they are not the same from the physical connection. But for the same kind of interface, if the output of A level standard conforms to the input of B level standard, then it is said that the output of A can drive the input of B. If vice versa, then it is said that the two level standards of A and B can drive each other. For example, the CMOS output can drive the TTL input, but not vice versa, because the TTL state 1 output is only greater than or equal to 2.4V, and can not reach the CMOS judgment state 1 needs to be greater than or equal to 3.5V; however, the LVTTL3V3 and LVCMOS3V3 can be driven by each other, because their outputs are able to satisfy the requirements of each other's input judgment.